Metal-Oxide-Semiconductor (MOS) electrically programmable read-only memories (EPROMS) frequently use memory cells that have electrically isolated gates (floating gates). These floating gates are typically completely surrounded by insulation and formed from a polycrystalline silicon (polysilicon) layer. Information is stored in the memory cells or devices in the form of charge on the floating gates. Charge is transported to the floating gates by a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc., depending on the construction of the cells. The cells are erased generally by exposing the array to ultraviolet radiation. An example of these cells can be found in U.S. Pat. Nos. 3,500,142; 3,660,819; 3,755,721; and 4,099,196. In some cases these cells are electrically erasable (EEPROM cells). An example of such a cell is shown in U.S. Pat. No. 4,203,158.
The invention of the present application is used with an EPROM cell, particularly one which is electrically erasable, commonly referred to as a "flash" EPROM cell.
Due to the nature and design of flash EPROM cells, the entire array must be erased in order to erase any one cell in that array. Generally, this has not been a problem in that each row (word line) is separately addressable and each column (bit line) is either separately addressable or can be addressed in groups of 8 (comprising 1 byte). Further, prior to erasing the entire array, each memory cell in that array must be preconditioned.
Preconditioning is the process whereby a memory cell is programmed prior to erasure to avoid over-erasing the cell which can cause leakage within that cell resulting in false data readings. This occurs when a cell in the zero state undergoes an erase operation whereby it can be driven into the depletion mode. The column sense amplifier can read this leakage current falsely as an erased cell. Therefore, proper preconditioning is necessary to avoid over erasing a single cell which can in turn cause an entire array to be defective.
When a row (wordline) is found to be defective by the manufacturer, it is desirable to be able to assign an alternate row to take its place. Using an alternate row can thus increase the yield of working memory chips. However, due to the need to precondition each memory cell in the array prior to erasing that array, it is necessary to be able to precondition each row in the array; those that are working as well as those determined to be defective in the manufacturing test stage.
The difficulty in preconditioning both good rows and bad rows is several fold. First of all, because an alternate row has been set to take the place of the bad row, it may be difficult to address or access the bad row without also accessing the alternate row. Secondly, even if one could separately address the bad row, if the defect which caused that row to be bad was due to a short between that row and a neighboring row, then merely addressing the first bad row would not be sufficient to be able to precondition (program) that first bad row because it would merely short to the neighbor just as it did during manufacturing test. Thirdly, it was previously believed to not be possible to precondition both bad rows simultaneously as it was felt that one of the two bad rows would predominate by stealing all the current thus allowing it to be preconditioned but not allowing the other bad row to be preconditioned thus still exposing the other bad row (and thus the entire array) to the over-erasure problem.